Stego System on Chip with LFSR based Information Hiding Approach

paper discusses about implementation of image steganographic system on Field Programmable Gate Array and the information hiding techniques in various images that are stored in the reconfigurable hardware and external memory. As a spatial domain steganography approach, Linear Feedback Shift Register (LFSR) method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different polynomial expressions have been implemented at the hardware level for hiding the secret data. Altera Cyclone II FPGA has been used to implement stego architecture. Synthesis report, Total time taken for hiding information at hardware level, Performance of reconfigurable hardware under various LFSR address generator schemes, MSE and PSNR issues are also discussed in this paper.