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big. LITTLE Architecture: Heterogeneous Multicore Processing
Author(s) -
Shubham Kamdar,
Neha Kamdar
Publication year - 2015
Publication title -
international journal of computer applications
Language(s) - English
Resource type - Journals
ISSN - 0975-8887
DOI - 10.5120/21034-3106
Subject(s) - computer science , architecture , multi core processor , computer architecture , data science , parallel computing , history , archaeology
ARM’s big.LITTLE architecture introduces a solution to optimize power consumption by selecting the core type most suitable for a level of processing load along with high performance. Using heterogeneous multi-core processing having high performance cortex-A15 with power efficient cortex-A7 is what big.LITTLE architecture follows to have power efficient system on chip which is demanded by today’s smart phones. For smooth functioning and effective data transferring big.LITTLE uses GIC-400 and CCI-400 interfaces to interface between two processors. Present smart phones using big.LITTLE technology having cluster migration as their operating mode. But using global task scheduling method as operating mode of smart phones in which cores gets individually activated or deactivated according to workload can give even further improvement in power consumption.

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