Low Power Domino Full Adder | Zendy

Payal Soni | Zendy; Shiwani Singh | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

Low Power Domino Full Adder

Author(s) -

Payal Soni,

Shiwani Singh

Publication year - 2014

Publication title -

international journal of computer applications

Language(s) - English

Resource type - Journals

ISSN - 0975-8887

DOI - 10.5120/16255-5866

Subject(s) - computer science , domino , adder , power (physics) , domino logic , domino effect , arithmetic , telecommunications , algorithm , logic gate , logic synthesis , law , mathematics , political science , biochemistry , chemistry , physics , logic family , quantum mechanics , catalysis , latency (audio)

With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better results in terms of power, delay and power-delay product. All the simulations have been performed on 45nm technology using tanner EDA tool version 13.0.

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research