Modified CPL Adiabatic Gated Logic MCPLAG based DPET DFF with XOR

The use of Adiabatic Logic in VLSI chip design has certainly promised positive aspects in terms of optimizing the power equations. In the reported work authors have extended their proposed CPLAG based ‘XOR’ implementation. The modified ‘XOR’ implementation is further configured to implement a dynamic positive edge triggered D flip flop. Both the reported circuits are functionally verified and found to be satisfactory to a high degree of signal integrity and accuracy. DFF circuit is further examined with different load, temperature range, transistor size and voltage levels. The results obtained from the proposed implementation of hybrid ‘XOR’ and DFF have showed good results. The average power at 1.5V, 180nm, 25C, 1fF load is 0.209nW and 2339nW for 0.8v, 40C for different run with Pclk_Q delay 0.2ns, input_Q delay 16μs, Qtrise 44.6μs, Qtfall 61μs, Qbtrise 4.54μs, Qbtfall 3μs with 50.9 zepto units PDP. The average power consumption for a conventional semi-adiabatic PFAL DFF is 35mW approx as compared to 0.1μW for the implemented DFF. General Terms Low Power, VlSI Design, CPL, Adiabatic Logic. Power delay product, fully adiabatic logic, semi adiabatic logic