A novel test scheme for detecting faulty recall margin cells for 6T-4C FeRAM | Zendy

Yohei UNEKI | Zendy; Shintaro Izumi | Zendy; Hiroto Kitahara | Zendy; Tomoki Nakagawa | Zendy; Koji Yanagida | Zendy; Shusuke Yoshimoto | Zendy; Hiroshi Kawaguchi | Zendy; Masahiko Yoshimoto | Zendy; Hiromitsu Kimura | Zendy; Kyoji Marumoto | Zendy; Takaaki Fuchikami | Zendy; Yoshikazu Fujimori | Zendy

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A novel test scheme for detecting faulty recall margin cells for 6T-4C FeRAM

Author(s) -

Yohei UNEKI,

Shintaro Izumi,

Hiroto Kitahara,

Tomoki Nakagawa,

Koji Yanagida,

Shusuke Yoshimoto,

Hiroshi Kawaguchi,

Masahiko Yoshimoto,

Hiromitsu Kimura,

Kyoji Marumoto,

Takaaki Fuchikami,

Yoshikazu Fujimori

Publication year - 2017

Publication title -

memoirs of the graduate schools of engineering and system informatics kobe university

Language(s) - English

Resource type - Journals

eISSN - 2434-0073

pISSN - 2185-5110

DOI - 10.5047/gseku.e.2016.002

Subject(s) - ferroelectric ram , margin (machine learning) , scheme (mathematics) , recall , test (biology) , computer science , reliability engineering , embedded system , psychology , real time computing , engineering , materials science , cognitive psychology , optoelectronics , machine learning , mathematics , geology , mathematical analysis , paleontology , dielectric , ferroelectricity

This paper proposes a novel test scheme that can detect faulty margin cells in non-volatile 6T-4C FeRAM (six-transistor four-capacitor ferroelectric random access memory). The FeRAM behaves as a non-volatile memory using spontaneous polarization characteristic of the ferroelectric capacitor. The datum is stored as a difference in the polarization direction, and is read out as potential difference of the polarization direction. The proposed test scheme can screen the faulty cells that have smaller recall margins by injecting offset voltage to the memory cell. The proposed scheme is evaluated by Monte Carlo simulations of 16,000 times. The proposed test scheme is possible to detect all fault cells by injecting the offset voltage of 100 mV in a 0.13 μm CMOS process.

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