Study of performance of Adiabatic Carry Look Ahead Adder Using Dynamic CMOS Logic

Performance of adiabatic carry look ahead adder using dynamic CMOS are studied and compared with Adiabatic carry look ahead adder using Pass Transistor. adiabatic carry look ahead adder using pass transistor has higher delay and lower power consumption while adiabatic carry look ahead adder using dynamic cmos logic has lower power dissipation and higher speed. adiabatic carry look ahead adder using dynamic cmos are design using 180 nm cmos technology and compared power dissipation and delay with respect to supply voltage and frequency. simulation result show that power dissipation of carry look ahead adder using dynamic cmos has higher performance comparison adiabatic CLA using pass transistor. simulation result show that adiabatic CLA using dynamic cmos reduce the power consumption 45% and delay reduce to 70% comparison to adiabatic CLA using pass transistor. IntroductionFor low power and higher speed circuit VLSI designer explore a new technology that dissipate low power and generate low noise. adiabatic logic using pass transistor is new approach that dissipate low power and generate low noise[24] but its speed is reduce comparison to other digital circuit so we proposed adiabatic logic using dynamic cmos that dissipate low power and generate low noise and show higher speed. In this paper comparative study of adiabatic CLA using pass transistor and adiabatic CLA using dynamic cmos. Dynamic CMOS logic is one of the promising circuit techniques for high speed operation [5-7]. An efficient decimal carry look ahead structure is to improve computation delay problem [8] . Static CMOS require 2N device for n fanin while Dynamic CMOS circuit uses N+1device for n fan-in Operation of dynamic CMOSThere are two mode of operation.1-Precharge,2Evaluation in the dynamic cmos design pull down network(PDN) is constructed exactly same as in complementary Prechargein the dynamic CMOS PMOS transistor is precharge gate and NMOS transistor is evaluation gate .when clock is zero(CLK=0) output node is precharge to Vdd by the PMOS transistor Mp while evaluate NMOS transistor is off so the pulldown path is disabled. evaluation transistor (NMOS) eliminates any static power dissipation that would be consumed by the precharge period. Evaluation – when CLK=1 precharge transistor (Mp) is off and evaluation transistor is on during this time output is discharge based on input value. if the input are such that PDN conduct then a low resistance path exist between output and GND and output is discharged to GND. If the PDN is off then precharge value is stored on the output capacitance CL. Once output node is discharge then it cannot be charged again till the next precharge operation.Output canbe high impedance state during the evaluation period if the pull down network is off Design of Adiabatic CLA using dynamic CMOShere we design the 4 bit adiabatic CLA using Dynamic CMOS .AND gate and OR gate using Dynamic CMOS logic .In the Dynamic CMOS logic design only higher mobility of transistor is used so the Dynamic CMOS circuit performance increase and due to absence of PMOS input capacitance also low .AND gate and OR gate circuit is given below . AND GATE USING DYNAMIC CMOS Study of performance of Adiabatic Carry Look Ahead Adder Using Dynamic CMOS Logic