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p-ZnTe thin film semiconductors have been successfully used as an absorber material to n-CdS window layer by effectively optimising the ZnTe absorber layer thickness. In order to create a two-terminal hetero-junction diode from the nand ptype materials, two ohmic electrical contacts are required. This was achieved by depositing n-CdS layers on glass/fluorine-doped tin oxide (FTO) conducting substrate and evaporating Au on p-ZnTe layer. The ZnTe layer was successfully electroplated on CdS thin film grown on glass/fluorine-doped tin oxide (FTO) conducting substrates. The device structures were subjected to heat treatment in air with and without CdCl2 surface treatment using temperature of 400C and duration of 10 minutes. The incorporation of the CdCl2 treatment led to enhancement in the solar cell efficiency. Solar cells developed from glass/FTO/n-CdS/p-ZnTe/Au device structure gave an open circuit voltage (Voc) of 450 mV, short circuit current density (Jsc) of 7.26 mAcm -2 and fill-factor (FF) of 0.31 resulting in ~1.0% efficiency (η) for n-CdS/p-ZnTe heterostructure annealed ordinarily in air. After treating the top surface of n-CdS/p-ZnTe heterostructure with CdCl2 solution, all the solar cell parameters improved with Voc of 480 mV, Jsc of 24.0 mAcm -2 and FF of 0.46 giving a total efficiency of ~5.3%. For the CdS/ZnTe heterostructures treated without and with CdCl2 solution, the rectification factors (RF) observed from the I-V characteristics under dark condition for these devices are 10 1.0 and 10 respectively. Both devices show ideality factors (n) in excess of 2.0 and the reverse saturation currents are 79.4 and 0.16 nA for heterojunction structures without and with CdCl2 treatment respectively. The improvement in the solar cell efficiency can be accredited to the integration of the CdCl2 treatment in the p-n junction cells. KeywordsSolar Cells, p-n Junction Diodes, n-CdS, Heterostructure, p-ZnTe, CdCl2 surface treatment.  ◆

Incorporation of CdCl2 surface treatment into the CdS/ZnTe hetero-junction solar cell device structures for efficiency improvement