Open AccessA 10-bit Current-steering DAC in 0.35-μm CMOS Process
Author(s) -
ZhiYuan Cui,
Hua-Lan Piao,
Namsoo Kim
Publication year - 2009
Publication title -
transactions on electrical and electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.201
H-Index - 18
eISSN - 2092-7592
pISSN - 1229-7607
DOI - 10.4313/teem.2009.10.2.044
Subject(s) - cascode , unary operation , cmos , decoding methods , bit (key) , current source , materials science , binary number , voltage , current (fluid) , fabrication , power (physics) , die (integrated circuit) , computer science , electronic engineering , electrical engineering , optoelectronics , physics , engineering , algorithm , amplifier , mathematics , arithmetic , quantum mechanics , pathology , medicine , combinatorics , nanotechnology , alternative medicine , computer security
A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-µm CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz .
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