System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec | Zendy

Xinwei Niu | Zendy; Jeffrey Fan | Zendy

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System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Author(s) -

Xinwei Niu,

Jeffrey Fan

Publication year - 2013

Publication title -

optics and photonics journal

Language(s) - English

Resource type - Journals

eISSN - 2160-889X

pISSN - 2160-8881

DOI - 10.4236/opj.2013.32b028

Subject(s) - computer science , codec , bottleneck , video processing , embedded system , computer hardware , hardware acceleration , adaptive multi rate audio codec , coding (social sciences) , energy consumption , direct memory access , real time computing , field programmable gate array , operating system , statistics , mathematics , speech processing , artificial intelligence , voice activity detection , ecology , transfer (computing) , biology

Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.

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