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Electromigration Performance of Fine-Pitch Copper Pillar Interconnections
Author(s) -
Ahmer Syed,
Christopher Berry,
D. Karthikeyan,
Patrick Thompson,
SeungHyun Chae
Publication year - 2012
Publication title -
imapsource proceedings
Language(s) - English
Resource type - Journals
ISSN - 2380-4505
DOI - 10.4071/isom-2012-thp11
Subject(s) - electromigration , miniaturization , materials science , thermal copper pillar bump , interconnection , copper , intermetallic , soldering , flip chip , current density , optoelectronics , current crowding , robustness (evolution) , electronic packaging , electronic engineering , composite material , metallurgy , current (fluid) , electrical engineering , nanotechnology , computer science , layer (electronics) , engineering , computer network , biochemistry , chemistry , adhesive , physics , alloy , quantum mechanics , gene
The miniaturization trend in electronic packaging continues to drive smaller and smaller chip-to-substrate interconnections with no reduction in IC operating temperature or device power in sight. These two factors (current density and temperature) make the electromigration lifetime of chip-to-package interconnections a critical consideration in package design. Of particular interest these days are the “fine pitch copper pillar” structures due to their very small size (30um dia or less). This paper presents interconnection lifetime and metallurgical data on the same which demonstrates the extreme robustness of these joints due largely to their reaching a fully reacted state in which no free solder exists in the conduction path thus providing electromigration performance like that of the base copper and intermetallic compounds. Joint resistance trends observed during stress testing are also discussed.

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