Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration | Zendy

Chien-Ying Wu | Zendy; Shang-Chun Chen | Zendy; Pei-Jer Tzeng | Zendy; John H. Lau | Zendy; Y. Y. Hsu | Zendy; JuiChin Chen | Zendy; Yu-Chen Hsin | Zendy; ChienChou Chen | Zendy; Shang-Hung Shen | Zendy; Cha-Hsin Lin | Zendy; Tzu-Kun Ku | Zendy; MingJer Kao | Zendy

Open Access

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Author(s) -

Chien-Ying Wu,

Shang-Chun Chen,

Pei-Jer Tzeng,

John H. Lau,

Y. Y. Hsu,

JuiChin Chen,

Yu-Chen Hsin,

ChienChou Chen,

Shang-Hung Shen,

Cha-Hsin Lin,

Tzu-Kun Ku,

MingJer Kao

Publication year - 2012

Publication title -

journal of microelectronics and electronic packaging

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.192

H-Index - 17

eISSN - 1555-8037

pISSN - 1551-4897

DOI - 10.4071/imaps.308

Subject(s) - wafer , materials science , plating (geology) , through silicon via , leakage (economics) , oxide , optoelectronics , silicon , plasma enhanced chemical vapor deposition , electronic engineering , metallurgy , engineering , geophysics , economics , macroeconomics , geology

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

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