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A Multistep Process for Thinning Individual Die to sub-35 μm Thickness
Author(s) -
Jeffrey Y. Thompson,
Gary Tepolt,
Livia Racz,
Chris Rogers,
Vincent P. Manno,
Robert D. White
Publication year - 2010
Publication title -
journal of microelectronics and electronic packaging
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.192
H-Index - 17
eISSN - 1555-8037
pISSN - 1551-4897
DOI - 10.4071/imaps.256
Subject(s) - die (integrated circuit) , wafer , lapping , chemical mechanical planarization , lamination , materials science , substrate (aquarium) , thinning , layer (electronics) , composite material , trimming , optoelectronics , mechanical engineering , engineering , nanotechnology , ecology , oceanography , geology , biology
The drive toward increased packaging density relies on die stacking. In order to maximize functional density, die are generally thinned on the wafer level. However, high-cost low-volume applications may not have full wafers available. Therefore, a method to thin individual die must be developed. In this article, a detailed and reliable process for thinning die to sub35 μm is outlined. The process consists of four steps: pseudo-wafer lamination, mechanical lapping, chemical mechanical planarization (CMP), and die release. A pseudo-wafer is created by adhering die to a glass substrate. Mechanical lapping is used to remove the bulk silicon and reduce die thickness to approximately 50 μm. CMP is used to attain thicknesses of sub35 μm and remove the subsurface damage layer from the die. This process can reliably produce die thinned to sub35 μm with ± 1.5-μm total thickness variation (TTV). The die are then released from the glass substrate and are handled using a customized vacuum carrier.

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