A Design Paradigm to Facilitate Multiple Parts from a Single Silicon Design

To reduce overall design complexity and cost for RAM, a design paradigm is discussed that is based on a single silicon device containing multiple, configurable interfaces with a common RAM core. This will help bring to market more devices that operate in extreme environments. The cost per die is higher due to the addition of the configurable interface, but yields a net reduction in overall engineering development time for a given product family by a factor of four to five. To demonstrate this design paradigm a family of five RAM chips built on a single silicon design is developed. They are designed for low-power consumption and highly reliable, fault-tolerant operation, while operating over a temperature range of −55 to +300 degrees C.