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As technology nodes progress to 16/14nm and beyond underfill materials are presented with the significantly challenging task of maintaining bump protection while ensuring low warpage for ultra low-K dielectric (ULK/ELK) integrity. This challenge is further complicated by the trend toward RoHS compliancy (lead-free) and an ever increasing die size (beyond 25x25mm). Through extensive research and testing, several specifically formulated underfill materials were determined acceptable solutions for these complex issues. As technology nodes progress to smaller processes high stress concentrations are seen at the dielectric layer during thermal cycling. This stress is a typical result of a high glass transition temperature (Tg) / high strength material that often leads delamination or a cracking failure mode of the thin dielectric layer. Too low of a Tg presents a high stress concentration on the bumps which once again constitutes failure, this time, however, the crack is typically seen at the bump location. This high stress concentration seen at the bumps is more significant when lead free bumps are considered due to their inherent fragile nature. Underfill materials must now be specifically optimized for variable package conditions to solve these failure modes for a large variation of package designs. Desired material properties must be quickly calculated using finite element methods. This paper will discuss solutions to typical failure modes currently seen in reliability testing of present and future technologies.

Packaging Materials for Flip Chip and WLP: Underfill Design Using FEM for FC-BGA, FC-CSP, and Moving Towards 2.5/3D.