Multi-scale materials data for 3D TSV stack performance simulation and model validation

Within a DFM type of methodology, the application of physics-based models for a multi-scale simulation of mechanical stress in 3D TSV-stacked products was proposed in [1]. Highly accurate multi-scale materials data are needed as input for this approach of simulation and for model validation. This paper focuses on the set of materials data for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation. Particularly the generation of materials data such as (local and effective) Young's modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. The nanoindentation method was developed further to measure local and effective elastic modulus values and Poisson ratio for micro-bump, TSV and BEoL stacks. TCAD simulations show significant influence of the copper microstructure on the charge carrier mobility in transistors [2]. To consider the orientation dependence of elastic properties of copper, nanoindentation with extremely low penetration depths was applied. A high-resolution in-situ technique was developed to determine “composite CTE” values for BEoL stacks. A free-standing cantilever containing the region of interest was extracted using the FIB technique, and imaged in a SEM at several temperatures. For model validation and calibration, local stress measurements are needed to determine the effect of the TSV/package-induced stress on the transistor performance. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM. For the first time, the strain in transistor channels will be reported as a function of the distance from the TSV, based on Convergent Beam Electron Diffraction (CBED) data.