Flip Chip Fine Pitch PBGA Yield Study | Zendy

Tim Pham | Zendy; B. Yeung | Zendy; Trent Uehling | Zendy; Brett Wilkerson | Zendy

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Flip Chip Fine Pitch PBGA Yield Study

Author(s) -

Tim Pham,

B. Yeung,

Trent Uehling,

Brett Wilkerson

Publication year - 2011

Publication title -

additional conferences (device packaging hitec hiten and cicmt)

Language(s) - English

Resource type - Journals

ISSN - 2380-4491

DOI - 10.4071/2011dpc-wp32

Subject(s) - materials science , yield (engineering) , flip chip , substrate (aquarium) , die (integrated circuit) , chip , composite material , electronic engineering , electrical engineering , nanotechnology , engineering , layer (electronics) , oceanography , adhesive , geology

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.

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