3D Passive Integrated Capacitors Towards Even Higher Integration

IPDIA is involved in Silicon based 3D-IPD advanced technology. This very flexible technology is using standard processing techniques to integrate passive components such as inductors, resistors or capacitors into a silicon substrate. 3D high-density capacitor is at the forefront of IPDIA development program. First process generation with 25nF/mm2 and second generation reaching 80nF/mm2 have been in production for several years. The third generation with multiple metal-insulator-metal (MIM) layer stacks in the pores is reaching 250nF/mm2 and is being qualified now. Intrinsic low parasitic elements of these capacitors (low ESR and ESL) make it very attractive for DC decoupling and very competitive with the ceramic technology. Assembly can be performed using standard reflow soldering and its low profile also allows PICS capacitor integration in embedded module board technology. Sensors, healthcare and medical applications can benefit from this new development. To enable even higher integration, development activities are now focused on the third and fourth generation of high-density capacitors targeting ambitious 1μF/mm2. In this presentation, main characteristics of the PICS high-density capacitors will be described emphasizing on its capability, main applications and advantages versus discrete components. Then, in a second part, challenges raised by the increase of the capacitor density while keeping an acceptable breakdown voltage will be discussed. This includes the integration of high-k materials with adequate electrode and the research for maximizing the 3D silicon surface.