Wafer Level Packaging Cost Modeling

Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.