Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System | Zendy

P. Nirmal Kumar | Zendy; S. Anandhi | Zendy; M. Elancheral | Zendy; J. Raja Paul Perinbam | Zendy

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Testing Virtual Reconfigurable Circuit Designed For A Fault Tolerant System

Author(s) -

P. Nirmal Kumar,

S. Anandhi,

M. Elancheral,

J. Raja Paul Perinbam

Publication year - 2007

Publication title -

journal of computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.161

H-Index - 28

eISSN - 1552-6607

pISSN - 1549-3636

DOI - 10.3844/jcssp.2007.934.938

Subject(s) - computer science , fault tolerance , embedded system , computer architecture , computer hardware , distributed computing

This research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails as open (iii) sensors fails as short circuit. The objective of this research is to test the desired optimal circuits evolved by decoding the configuration bit streams. The logic simulation tool used to perform fault simulation is AUSIM (Auburn University Simulator)

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