A Novel Strategy for Formal Verication of Asynchronous Circuit Design in PAiD tool

EDA has been proposed for a long time as a category of reliable software tools for designing electronic systems. Although some of them have been considered as powerful tools for asynchronous circuits, a prominent approach to cope with the biggest defect of synchronous circuits: clock distribution issue, researches in verifying the correctness of those circuits are still limited. Therefore, an enhanced version of PAiD, an EDA tool that has been developed at Ho Chi Minh City University of Technology (HCMUT), will be proposed in this work along with case studies. It will enable engineers not only design, synthesize asynchronous circuits but also verify them. Furthermore, a good strategy to improve the verifying performance is also discussed.