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We describe the optimum design of an execution stage for embedded processors. The execution stage is the core of embedded processors to treat basic applications for multimedia, communication and control. Considering algorithms in running such applications, the design principle of embedded processors is to achieve reliability, precision, low power, high speed and fast throughput altogether. However, it is hard to sufficiently clear the design principle by existing microprocessor technology. The one of difficult issues is the mixed sequence of integer and FP (floating point) arithmetic instructions. The different latencies of these instructions in a processor’s execution stage surely make the pipelined processing disturb and degrade throughput. The solution for this problem in this study is a wave-pipelined MFU (multifunctional unit) that is the multifunctionalization and wave-pipelining of different FUs (functional units). The high speed characteristic of wave-pipeling guarantees the reliability of processor behavior that is free from timing error. Thus, the waved MFU agrees well with overall trade-off design. In order to complement the shortage of the standard CAD tools, we explored the HS/SW (hardware/software) co-design for the waved MFU. Experimental results by using a 0.18-m CMOS standard cell technology showed the usefulness of this approach.

Design of the Optimum Execution Stage of Embedded Processors