Open AccessALD-ZrO2 gate dielectric with suppressed interfacial oxidation for high performance MoS2 top gate MOSFETs
Author(s) -
Wen Hsin Chang,
Naoya Okada,
Masayo Horikawa,
Takahiko Endo,
Yasumitsu Miyata,
Toshifumi Irisawa
Publication year - 2021
Publication title -
japanese journal of applied physics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.487
H-Index - 129
eISSN - 1347-4065
pISSN - 0021-4922
DOI - 10.35848/1347-4065/abd6d9
Subject(s) - materials science , atomic layer deposition , annealing (glass) , optoelectronics , dielectric , monolayer , metal gate , gate dielectric , high κ dielectric , capacitance , nanotechnology , gate oxide , layer (electronics) , electrical engineering , metallurgy , electrode , transistor , chemistry , voltage , engineering
To enhance the feasibility of 2-dimensional transition metal dichalcogenides (TMDCs) channels in future nano-electronic and optoelectronic devices, a top gate device structure fabricated with very-large-scale-integration compatible process is mandatory. High- κ dielectric ZrO 2 has been directly deposited on MoS 2 through low-temperature atomic layer deposition (ALD) without any surface protection layers. The uniform growth of ZrO 2 on MoS 2 was confirmed to be caused by the physical adsorption, resulting in the suppressed interfacial oxidation and the reduced damage of monolayer (1L) MoS 2 channel. Low thermal budget post-deposition annealing was found to be effective for reducing interfacial traps between ZrO 2 and MoS 2 interface, thus enhancing the device performances of 1L MoS 2 nMOSFETs. Low capacitance equivalent thickness (CET) of ZrO 2 of 2.3 nm has been achieved while maintaining decent device performance, indicating low-temperature ALD is promising for future TMDC top gate devices with a high-quality interface and thin CET.