Design and FPGA Implementation of Dual Scan two Dimensional Discrete Wavelet transforms

In this paper, hardware architectures for two dimensional discrete wavelet transform (2-D DWT) are examined, the 4-input/4-output Dual Scan architecture for one-level DWT is presented, then by using the pipelined architecture and parallel method, the one-level architecture is developed to perform a complete dyadic decomposition of NXN image in multi-level 2-D DWT. After that the internal memory sizes that are needed to design the proposed architectures and the proper fixed point word length are determined. The proposed architectures are down loaded in to FPGA board (Spartan-3E) to calculate the die area and the critical path of these architectures. The main advantage of Dual Scan method is high reduction in the time delay to perform the architecture.