VLSI Architecture for Real Time IWT

In this paper, the design of new real time integer to integer lifting based wavelet transform IWT architecture is focused. An efficient design method is proposed to construct an integrated programmable VLSI architecture that can operate as forward or backward IWT in pipeline fashion. The layout VLSI integrated structure is simple, modular, and cascadable for computation of wavelet transform based on 5/3 biorthogonal filters. The architecture is optimal with respect to both area and time and independent of the size of the input signal without necessitate to memory. The lifting steps adapted to be causal and the proposed architecture is suitable to be used in the real time processing applications. The critical path of the architecture is equal to critical path of one lifting step. The numerical precision has been established using simulink model. Experimental tests have been made with 8-bit signed two's complement integer numbers. Based on the experimental result observations, the data path width of proposed architecture is fixed at 10 bits.