Open AccessBrain-Inspired Hardware Solutions for Inference in Bayesian Networks
Author(s) -
Leila Bagheriye,
Johan Kwisthout
Publication year - 2021
Publication title -
frontiers in neuroscience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.499
H-Index - 102
eISSN - 1662-4548
pISSN - 1662-453X
DOI - 10.3389/fnins.2021.728086
Subject(s) - computer science , stochastic computing , inference , bayesian network , implementation , field programmable gate array , bayesian inference , bayesian probability , computer architecture , computer engineering , digital electronics , electronic circuit , computer hardware , artificial intelligence , artificial neural network , electrical engineering , programming language , engineering
The implementation of inference (i.e., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required by floating-point operations. A departure from conventional computing systems to make use of the high parallelism of Bayesian inference has attracted recent attention, particularly in the hardware implementation of Bayesian networks. These efforts lead to several implementations ranging from digital circuits, mixed-signal circuits, to analog circuits by leveraging new emerging nonvolatile devices. Several stochastic computing architectures using Bayesian stochastic variables have been proposed, from FPGA-like architectures to brain-inspired architectures such as crossbar arrays. This comprehensive review paper discusses different hardware implementations of Bayesian networks considering different devices, circuits, and architectures, as well as a more futuristic overview to solve existing hardware implementation problems.