Open AccessIntroducing Primality Testing Algorithm with an Implementation on 64 bits RSA Encryption Using Verilog
Author(s) -
Rehan Shams,
Fozia Hanif Khan,
Umair Jillani,
Muhammad Umair
Publication year - 2018
Publication title -
sir syed university research journal of engineering and technology
Language(s) - English
Resource type - Journals
eISSN - 2415-2048
pISSN - 1997-0641
DOI - 10.33317/ssurj.v2i1.68
Subject(s) - primality test , computer science , encryption , verilog , cryptography , field programmable gate array , key (lock) , algorithm , advanced encryption standard , public key cryptography , embedded system , prime (order theory) , computer hardware , mathematics , computer network , operating system , combinatorics
A new structure to develop 64-bit RSA encryption engine on FPGA is being presented in this paper that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i.e. key generation, encryption and decryption. This procedure also requires random generation of prime numbers, therefore, we are proposing an efficient fast Primality testing algorithm to meet the requirement for generating the key in RSA algorithm. We use right-to-left-binary method for the exponent calculation. This reduces the number of cycles enhancing the performance of the system and reducing the area usage of the FPGA. These blocks are coded in Verilog and are synthesized and simulated in Xilinx 13.2 design suit.