LARGE AREA SEMI-PERMEABLE ENCAPSULATION MEMBRANES USING CARBON NANOTUBE COMPOSITES

A batch-fabrication methodology to create large area vacuumsealed cavities on top of silicon substrates is reported. This process uses a semi-permeable membrane made of carbon nanotubes (CNTs) and polysilicon. The dense forest of CNTs, conformally coated with polysilicon by low pressure chemical vapor deposition (LPCVD), functions as the semi-permeable membrane. When the top surface is opened via plasma etching of polysilicon, the membrane is penetrable to liquid and vapor. Hydrofluoric acid (HF) vapor is used to etch the underlying oxide before sealing the film with another LPCVD of polysilicon, rendering it impermeable. Sealed areas of more than 1x1 mm have been fabricated. INTRODUCTION Microelectromechanical systems (MEMS), which function as sensors or actuators, have undergone considerable growth in the past two decades. One of the key developments has been the miniaturization of MEMS, making it possible to integrate their processing with that of integrated circuit (IC) processing to reduce the costs of manufacturing and packaging [1]. However, a key difference between MEMS and IC devices is that MEMS require some form of interaction with their environments for signal processing. This can be problematic when considering process flow compatibility. The key issue for MEMS process development is the packaging of the devices, which is often the primary barrier to the commercialization of MEMS devices. It also tends to contribute to up to 70% of the total cost for a MEMS device development cycle [2]. Due to the widely varying types of MEMS device materials and applications, a universally adopted industry standard remains elusive. Pressure, chemical, or fluidic sensors should to be open to the environment in order to function. On the other hand, accelerometers, gyroscopes, or oscillators should be hermetically sealed, sometimes with an anti-stiction agent and/or buffer gas [3]. Moisture penetration may also lead to corrosion within the package. One trend in industry packaging methodologies is the shift from die level packaging to wafer level packaging. Die level encapsulation involves dicing the chips on a wafer then packaging them individually with separate substrates. The drawbacks to this approach include special handling requirements so as to not damage the MEMS devices and reduced throughput since individual dies must first be packaged then tested for meeting performance specifications. Wafer level packaging mitigates a number of issues in die level packaging [4]. Importantly, incorporating encapsulation into the device fabrication steps prior to dicing provides an inherent protective lid for the MEMS structures during fabrication and back-end assembly. The wafer level encapsulation may be formed by interfacial bonding between the device substrate and a separate sealing wafer or by thin film deposition with the latter approach offering savings in material costs. Thin film encapsulation also eliminates the need for aligning separate wafers as well as the seal ring around each device, thereby increasing available space to enhance yield and throughput. Lastly, the lower topography of the packaged devices permits post encapsulation processing. The nature of thin films can limiting compared to bonded caps when considering the strength and size of the membrane, since these films may collapse or break under vacuum loads. Some thin film processes use the permeability of that membrane to provide a pathway for etchants to sacrificial layers, and they must be sealed afterward. Other thin films may simply be patterned with a small channel near the base in lieu of permeability [5]. In either case, for larger areas it’s often necessary to bolster the membrane with a hard film like silicon nitride, which may be problematic for processing due to slow deposition. Polysilicon is one such material that can be made permeable for thicknesses around less than 1μm [6,7]. However, incorporating this into a fabrication process requires numerous steps of doping, annealing, hard mask under layers, etc. that can be tedious. Thickness and area limitations are also an issue. However, combining polysilicon with another material such as CNTs opens possibilities to use thicker films for larger areas. The results presented here aim to improve the flexibility in designing the thickness and strength of encapsulation membranes compared to other thin film approaches. The concept of using a composite film of polysilicon and CNTs is discussed in the following section. CONCEPT CNTs are attractive materials for a number of reasons. They may be grown with very large aspect ratios and possess semiconducting properties along with good mechanical strength and self-alignment when grown in a forest. In this paper’s process CNT height may be set anywhere from 5μm to 50μm with short processing times, with CNTs serving as a skeletal framework for deposited encapsulation films. Moreover, the inclusion of CNTs into a composite film generates a natural porosity in the film due to the spacing between individual CNTs. Thus, a semi-permeable membrane forms by coating the CNT forest with a material like polysilicon. Fig. 1 below shows a schematic of the composite film.