Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

Multiple gate structures (MuGFETs) are known to be one of the most promising alternatives in order to increase the transistor performance for sub 22nm technology nodes [1]. The higher electrostatic channel control due to the presence of more than one gate results in a reduced short-channel effect. Additionally, the gate dielectric thickness has been a limitation for this scalability by an unacceptable increase of the gate leakage current [2]. As a result the integration of high-k dielectrics as gate insulator has been shown to be an alternative yielding a gate leakage current reduction [3]. The incorporation of nitrogen into these high-k materials can improve their thermal stability, reducing the dopant penetration and allowing further equivalent oxide thickness (EOT) scaling [4]. Alternative gate materials have also been studied to achieve a proper threshold voltage (VT) setting in both nand p-channel devices in high-performance CMOS applications [5]. Metal gate work function engineering has been shown an attractive technique for VT engineering whereby the poly-Si gate material is replaced by metal gate electrodes [6-7]. For a MuGFET technology titanium nitride (TiN) has been widely studied, showing low resistivity and a mid gap work function for both transistor types [8-10]. This effective work function can be tuned by varying its thickness, although a thicker TiN metal gate introduces a higher interface trap density and a correspondingly lower mobility [11]. MuGFET structures also present an attractive behavior for analog applications with a reduced drain output conductance and an extremely large Early voltage value. Moreover, a quasi-ideal subthreshold slope and a better ratio between on-off current were also observed [12-16]. Based on that, the aim of this work is to investigate the analog performance of SOI MuGFETs with different TiN metal gate electrode thicknesses and high-k dielectrics.