Memory-aware Workload Balancing Technique based on Decision Trees for Parallel HEVC Video Coding
Author(s) -
Iago Storch,
Bruno Zatt,
Luciano Agostini,
Guilherme Corrêa,
Daniel Palomino
Publication year - 2020
Publication title -
journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v15i3.96
Subject(s) - computer science , workload , speedup , coding (social sciences) , multiprocessing , parallel computing , exploit , algorithmic efficiency , computer engineering , operating system , statistics , mathematics , computer security
Digital Object Identifier 10.29292/jics.v15i3.96 Abstract— Video coding applications demand high computational effort to achieve high compression rates at a low perceptual quality expense. In order to reach acceptable encoding time for such applications, modern video coding standards have been employing parallelism approaches to exploit multiprocessing platforms, such as the tiling tool from HEVC standard. When employing Tiles, each frame is divided into rectangularshaped regions, which can be encoded independently. However, although it is possible to distribute the data equally among the processing units when using Tiles, balancing the workload among processing units poses significant challenges. Therefore, this paper proposes a workload balancing technique aiming to speed up the HEVC parallel encoding using Tiles. Unlike other literature works, the proposed solution uses a novel approach employing static uniform tiling to avoid memory management difficulties that may emerge when dynamic tiling solutions are employed. The proposed technique relies on workload distribution history of previous frames to predict the current frame’s workload distribution. Then, the proposed technique balances the workload among Tiles by employing a workload reduction scheme based on decision trees in the coding process. Experimental tests show that the proposed solution outperforms the standard uniform tiling, and it is competitive with related works in terms of speedup. Moreover, the solution optimizes resource usage in multiprocessing platforms, presents a negligible coding efficiency loss, and avoids increasing memory bandwidth usage by 9.8%, on average, when compared to dynamic tiling solutions, which can impact the performance in memoryconstrained platforms significantly.
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