Open AccessDESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION
Author(s) -
Md. Shabiul Islam,
M.S. Bhuyan,
M. Salim Beg,
Masuri Othman
Publication year - 2017
Publication title -
asean journal on science and technology for development
Language(s) - English
Resource type - Journals
eISSN - 2224-9028
pISSN - 0217-5460
DOI - 10.29037/ajstd.211
Subject(s) - vhdl , computer science , discrete cosine transform , very large scale integration , image compression , lossless compression , design flow , abstraction , digital signal processing , software , embedded system , computer hardware , computer architecture , chip , image processing , process (computing) , data compression , image (mathematics) , field programmable gate array , programming language , artificial intelligence , telecommunications , philosophy , epistemology
This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT) to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.). The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip
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