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Performance and error analysis of Knill's postselection scheme in a two-dimensional architecture
Author(s) -
Ching–Yi Lai,
Gerardo A. Paz-Silva,
Martin Suchara,
Todd A. Brun
Publication year - 2014
Publication title -
quantum information and computation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.504
H-Index - 73
ISSN - 1533-7146
DOI - 10.26421/qic14.9-10-7
Subject(s) - postselection , computer science , qubit , algorithm , error detection and correction , quantum computer , word error rate , quantum error correction , noise (video) , theoretical computer science , quantum , physics , quantum mechanics , quantum entanglement , speech recognition , artificial intelligence , image (mathematics)
Knill demonstrated a fault-tolerant quantum computation scheme based on concatenated error-detecting codes and postselection with a simulated error threshold of 3% over the depolarizing channel. We show how to use Knill's postselection scheme in a practical two-dimensional quantum architecture that we designed with the goal to optimize the error correction properties, while satisfying important architectural constraints. In our 2D architecture, one logical qubit is embedded in a tile consisting of 5×5 physical qubits. The movement of these qubits is modeled as noisy SWAP gates and the only physical operations that are allowed are local one- and two-qubit gates. We evaluate the practical properties of our design, such as its error threshold, and compare it to the concatenated Bacon-Shor code and the concatenated Steane code. Assuming that all gates have the same error rates, we obtain a threshold of 3:06 × 10-4 in a local adversarial stochastic noise model, which is the highest known error threshold for concatenated codes in 2D. We also present a Monte Carlo simulation of the 2D architecture with depolarizing noise and we calculate a pseudo-threshold of about 0:1%. With memory error rates one-tenth of the worst gate error rates, the threshold for the adversarial noise model, and the pseudo-threshold over depolarizing noise, are 4:06 × 10-4 and 0.2%, respectively. In a hypothetical technology where memory error rates are negligible, these thresholds can be further increased by shrinking the tiles into a 4 × 4 layout.

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