CROSSTALK AND DISCONTINUITIES REDUCTION ON MULTI-MODULE MEMORY BUS BY PARTICLE SWARM OPTIMIZATION

Due to high-density routing under the CPU and DIMM areas, the original design of even and odd mode characteristic impedances changes. The occurrence of multi-drop problem between the CPU and memory chip causes over- and under-driven that reduce the eye opening. Furthermore, the difierent phase velocities of even- and odd-modes cause timing jitter at the receiver end. This paper proposes two steps to solve the complex issue of signal integrity for the multi-module memory bus. First, particle swarm optimization (PSO) is used to tune the characteristic impedance of the transmission line and on-die termination (ODT) values to improve transmission line impedance changes to obtain maximum power delivery. The fltness function of the algorithm is deflned by selecting the minimum re∞ection coe-cient at the driver side and maximum the transmission coe-cient at the receiver side to reduce the over- and under-driven Second, the timing jitter can be reduced by placing a capacitor to compensate for the velocity difierence caused by difierent propagation modes. Finally, signal integrity enhancements for the DDR3 are verifled by measuring S parameters in the frequency domain and postprocessed eye diagrams in the time domain.