Short-circuit robustness of parallel SiC MOSFETs and fail-safe mode strategy

Silicon carbide (SiC) power MOSFETs exhibit some key differences compared with Silicon (Si) MOSFETs and IGBTs. In particular, both their intrinsic (i.e., material technology related) and extrinsic (i.e., device generation related) features-set implies, on the one hand, higher stress levels of the single chip during a short-circuit and, on the other hand, a greater spread in the value of some of the main electro-thermal parameters affecting the transistor performance during this stressful transient event. Thus, this paper proposes a thorough experimental analysis of the short-circuit robustness of parallel connected SiC Power MOSFETs, taking into account the actual distribution in their parameters. The overall aim is twofold: producing de-rating guidelines for multi-chip structures and developing validated strategies for ensuring new and original soft-fail (or fail-safe) modalities in the application, as a result of both single and repetitive pulse degradation.