Visual software system for memory interleaving simulation
Author(s) -
Katarina Milenković,
Žarko Stanisavljević,
Jovan Djordjević
Publication year - 2017
Publication title -
serbian journal of electrical engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.133
H-Index - 5
eISSN - 2217-7183
pISSN - 1451-4869
DOI - 10.2298/sjee1701051m
Subject(s) - reset (finance) , computer science , interleaving , set (abstract data type) , software , memory hierarchy , simulation software , hierarchy , state (computer science) , representation (politics) , simulation , operating system , programming language , market economy , politics , political science , financial economics , law , economics , cache
This paper describes the visual software system for memory interleaving simulation (VSMIS), implemented for the purpose of the course Computer Architecture and Organization 1, at the School of Electrical Engineering, University of Belgrade. The simulator enables students to expand their knowledge through practical work in the laboratory, as well as through independent work at home. VSMIS gives users the possibility to initialize parts of the system and to control simulation steps. The user has the ability to monitor simulation through graphical representation. It is possible to navigate through the entire hierarchy of the system using simple navigation. During the simulation the user can observe and set the values of the memory location. At any time, the user can reset the simulation of the system and observe it for different memory states; in addition, it is possible to save the current state of the simulation and continue with the execution of the simulation later. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. III44009
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