FPGA realization of Farrow structure for sampling rate change | Zendy

Bogdan Markovic | Zendy; Jelena Ćertić | Zendy

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FPGA realization of Farrow structure for sampling rate change

Author(s) -

Bogdan Markovic,

Jelena Ćertić

Publication year - 2016

Publication title -

serbian journal of electrical engineering

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.133

H-Index - 5

eISSN - 2217-7183

pISSN - 1451-4869

DOI - 10.2298/sjee1601083m

Subject(s) - realization (probability) , field programmable gate array , sampling (signal processing) , interpolation (computer graphics) , lagrange polynomial , signal (programming language) , computer science , block (permutation group theory) , digital signal processing , integer (computer science) , polynomial , mathematics , algorithm , computer hardware , telecommunications , statistics , mathematical analysis , geometry , frame (networking) , detector , programming language

In numerous implementations of modern telecommunications and digital audio systems there is a need for sampling rate change of the system input signal. When the relation between signal input and output sampling frequencies is a fraction of two large integer numbers, Lagrange interpolation based on Farrow structure can be used for the efficient realization of the resample block. This paper highlights efficient realization and estimation of necessary resources for polynomial cubic Lagrange interpolation in the case of the demand for the signal sampling rate change with the factor 160/147 on Field-Programmable Gate Array architecture (FPGA). [Projekat Ministarstva nauke Republike Srbije, br. TR-32023 i br. TR-32028

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