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In numerous implementations of modern telecommunications and digital audio   systems there is a need for sampling rate change of the system input signal.   When the relation between signal input and output sampling frequencies is a   fraction of two large integer numbers, Lagrange interpolation based on Farrow   structure can be used for the efficient realization of the resample block.   This paper highlights efficient realization and estimation of necessary   resources for polynomial cubic Lagrange interpolation in the case of the   demand for the signal sampling rate change with the factor 160/147 on   Field-Programmable Gate Array architecture (FPGA). [Projekat Ministarstva   nauke Republike Srbije, br. TR-32023 i br. TR-32028

FPGA realization of Farrow structure for sampling rate change