Open AccessPerformance evaluation of high speed compressors for high speed multipliers
Author(s) -
N. Ravi,
Rao Subba,
T. Jayachandra Prasad
Publication year - 2011
Publication title -
serbian journal of electrical engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.133
H-Index - 5
eISSN - 2217-7183
pISSN - 1451-4869
DOI - 10.2298/sjee1103293n
Subject(s) - gas compressor , adder , multiplier (economics) , power–delay product , computer science , digital signal processing , power consumption , energy consumption , computer hardware , electronic engineering , power (physics) , electrical engineering , engineering , cmos , physics , mechanical engineering , quantum mechanics , economics , macroeconomics
This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25°C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only
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