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Second-order sigma-delta modulator in standard cmos technology
Author(s) -
D. Milovanovic,
Milan Savić,
Miljan Nikolic
Publication year - 2004
Publication title -
serbian journal of electrical engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.133
H-Index - 5
eISSN - 2217-7183
pISSN - 1451-4869
DOI - 10.2298/sjee0403037m
Subject(s) - delta sigma modulation , cmos , swing , electrical engineering , bandwidth (computing) , electronic engineering , clock rate , dynamic range , engineering , physics , telecommunications , acoustics
As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 µm technology

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