Complexity reduction of Toffoli networks based on FDD

Synthesis of switching functions by Toffoli gates has become a very important research topic in the last years, since Toffoli gates are used in the synthesis of reversible circuits. Early methods based on the truth-table representation of Boolean functions are applicable to functions with a relatively small number of variables. Later on, methods for synthesis by Toffoli gates based on decision diagrams (BDDs, FDDs or OKFDDs) were introduced and applied to the synthesis of both reversible and irreversible functions. This paper presents a method for the reduction of the number of lines and gates in the Toffoli gate realization of Boolean functions based on their Functional Decision Diagram (FDD) representation. Experiments show that, when the proposed reduction is used, the realization of the given function based on FDD will, on the average, be smaller in terms of the number of lines and the number of gates than the realizations based on an OKFDD, an optimal BDD or based on a FDD by using previously defined algorithms.