An overview of on-chip buses

The electronics industry has entered the era of multi-milli on-gate chips, and thereXs no turning back. This technology promises new levels of integration on a single chip, called the System-on-a-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a singl e chip, may number well into the high tens within the next decade, given the current r ate of advancements, (1). Interconnection networks in such an environment are, therefore, becoming more and more important (2). Currently, on-chip interconnection ne tworks are mostly imple- mented using buses. For SoC applications, design reuse becomes easier if standard internal connection buses are used for interconnecting com ponents of the design. De- sign teams developing modules intended for future reuse can design interfaces for the standard bus around their particular modules. This allows f uture designers to slot the reuse module into their new design simply, which is also based around the same stan- dard bus (3). In this paper we give an overview of the more popular on-chip bus-based interconnection networks such as AMBA, Avalon, CoreConnect, STBus, Wishbone, etc. The main characteristics of the considered buses in res pect to topology, arbitration method, bus-width, and types of data transfers are discusse d.