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New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project
Author(s) -
Julian Maxime Mendez,
Sophie Baron,
A. Caratelli,
Pedro Leitao
Publication year - 2018
Publication title -
cern document server (european organization for nuclear research)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.22323/1.313.0083
Subject(s) - field programmable gate array , chipset , application specific integrated circuit , computer science , embedded system , vhdl , context (archaeology) , gigabit , engineering , chip , telecommunications , paleontology , biology
The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

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