Open AccessA timing macro model for performance optimization of CMOS logic circuits.
Author(s) -
Roger Shum
Publication year - 2018
Language(s) - English
Resource type - Dissertations/theses
DOI - 10.22215/etd/1992-02142
Subject(s) - macro , cmos , computer science , logic model , computer architecture , electronic engineering , electronic circuit , engineering , electrical engineering , programming language , sociology , social science