Open AccessDesign and Implementation of High Speed 16x16 CMOS Vedic Multiplier
Author(s) -
Praveen Kumar Sharma,
Gajendra Sujediya
Publication year - 2018
Publication title -
international journal of electrical electronics and computers
Language(s) - English
Resource type - Journals
ISSN - 2456-2319
DOI - 10.22161/eec.3.3.2
Subject(s) - multiplier (economics) , cmos , computer science , arithmetic , mathematics , electrical engineering , engineering , economics , keynesian economics
In today scenario digital circuits are become more and more complex because of long arithmetic calculations but with the help of Vedic mathematics that calculations can become easy and fast. To make multiplier we have different techniques, in this paper we design 16x16 CMOS multiplier using Vedic mathematics technique. Keywords—Multiplier, Vedic Mathematics, CMOS, 16x16 multiplier.
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