
Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array.
Author(s) -
Mark Walter Learn
Publication year - 2010
Language(s) - English
Resource type - Reports
DOI - 10.2172/984165
Subject(s) - field programmable gate array , computer science , embedded system , virtex , cache , multi core processor , computer architecture , parallel computing