Open AccessDelay locked loop integrated circuit.
Author(s) -
Robert W. Brocato
Publication year - 2007
Publication title -
osti oai (u.s. department of energy office of scientific and technical information)
Language(s) - English
Resource type - Reports
DOI - 10.2172/921727
Subject(s) - application specific integrated circuit , delay locked loop , clock skew , integrated circuit , computer science , phase locked loop , electronic engineering , waveform , ibm , cmos , synchronization (alternating current) , computer hardware , clock domain crossing , synchronous circuit , engineering , electrical engineering , clock signal , jitter , voltage , topology (electrical circuits) , physics , optics
This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz
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