Novel method for making semiconductor chips. Seventh quarterly and final report, January 7, 1995--May 7, 1995

Work under DOE Grant No. DE-FG47-93R701314, to investigate a Novel Process for Fabricating MOSFET Devices, has progressed to a point where feasibility of producing MOSFETS using Chromium Disilicide Schottky barrier junctions at Source and Drain has been shown. Devices fabricated, however, show inconsistent operating characteristics from device to device, and further work is required to overcome the defects. Some fabrication procedures have produced a relatively high, (e.g., ninety-five (95%) percent), yield of devices on a substrate which show at least some transistor action, while others have resulted in very low yield, (e.g., five (5%) percent). Consistency of results from device to device is less than desired. However, considering that the University of Nebraska at Lincoln (UNL) Electrical Engineering Fabrication Lab is not what industry can provide, it is reasonable to project that essentially one-hundred (99.99+%) percent yield should be achievable in an industrial setting because of the simplicity in the fabrication procedure