Open AccessSingle event gate rupture in thin gate oxides
Author(s) -
F W Sexton,
D M Fleetwood,
M R Shaneyfelt,
P E Dodd,
G L Hash
Publication year - 1997
Language(s) - English
Resource type - Reports
DOI - 10.2172/491556
Subject(s) - gate oxide , electric field , oxide , materials science , event (particle physics) , voltage , optoelectronics , electrical engineering , electronic circuit , scaling , and gate , field (mathematics) , integrated circuit , logic gate , gate voltage , engineering , metallurgy , physics , mathematics , transistor , geometry , quantum mechanics , pure mathematics
As integrated circuit densities increase with each new technology generation, both the lateral and vertical dimensions shrink. Operating voltages, however, have not scaled as aggressively as feature size, with a resultant increase in the electric fields within advanced geometry devices. Oxide electric fields are in fact increasing to greater than 5 MV/cm as feature size approaches 0.1 {micro}m. This trend raises the concern that single event gate rupture (SEGR) may limit the scaling of advanced integrated circuits (ICs) for space applications. The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for thin gate oxides. Critical field for SEGR increases with decreasing oxide thickness, consistent with an increasing intrinsic breakdown field