The bulk-store module for FASTBUS memory applications. Final technical report

The FASTBUS system specification for high-energy physics and other data system applications defines a large address space in which support modules may reside on connected segments. Experiments in the physical sciences using FASTBUS indicate that the spectrum of support modules must continue to grow and be extended in capability. The features of the FASTBUS protocol can be effectively used to help increase the available data storage space and improve performance for large-memory configurations such as the Bulk-Store Module (BSM). To this end, the module design features automatic address-only histogramming, memory interleaving at the module level, and circular data buffering as well as normal random memory access. This report describes the components of the 32-bit, 8 megaword error-correcting memory module for the FASTBUS data system designed under a Phase II SBIR grant through the U.S. Department of Energy, Division of Energy Research. A key feature of the BSM is the design of a single-chip application-specific integrated circuit (ASIC) to interface the FASTBUS protocol to any slave application, and particularly to the BSM. The FASTBUS Slave Interface (FSI) design contains features that help the BSM perform its specified tasks, in addition to providing a complete interface to the FASTBUS protocol, including broadcast and advanced mode response. We further cover the chronology of the Phase II work effort and our experiences with two ASIC manufacturers in attempting to complete the actual fabrication of the FSI chips. The appendices of this report contains the functional description and design schematics of the BSM, and of the FSI ASICS in two different semiconductor technologies