Exploring formal verification methodology for FPGA-based digital systems.

With the Life Extension Programs (LEPs), many nuclear weapon (NW) analog electronic components are being replaced by modern digital devices, increasing system complexities dramatically. Ensuring the reliability, security, and robustness of these upgraded systems is critically important. Many custom hardware systems throughout the NW operations space rely on Field-Programmable Gate Arrays (FPGAs) to implement sophisticated logic. Effective verification, while increasing confidence, can reduce the overall effort in system debugging and testing. This work explored Formal Verification (FV) of trusted FPGA-based hardware designs through the use of novel algorithms. The algorithms developed support the analysis of critical digital components, such as memory, with mathematical reasoning from automated theorem proving and model checking. Such verification will detect race conditions and corner cases at an early stage, eliminating system failure and instability during operation. This work was funded by the Laboratory Directed Research and Development (LDRD) office at Sandia National Laboratories. Exploring Formal Verification Methodology for FPGA-based Digital Systems