Open AccessThree wafer stacking for 3D integration.
Author(s) -
K. Douglas Greth,
C. W. Ford,
Jeffrey Lantz,
Subhash L. Shindé,
Robert P. Timon,
Todd Bauer,
Dale L. Hetherington,
Carlos Anthony Sanchez
Publication year - 2011
Publication title -
osti oai (u.s. department of energy office of scientific and technical information)
Language(s) - English
Resource type - Reports
DOI - 10.2172/1031299
Subject(s) - stacking , wafer , materials science , reticle , process integration , optoelectronics , process (computing) , computer science , nanotechnology , electronic engineering , process engineering , engineering , chemistry , operating system , organic chemistry
Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation
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