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Using reconfigurable functional units in conventional microprocessors.
Author(s) -
Arun Rodrigues
Publication year - 2010
Publication title -
osti oai (u.s. department of energy office of scientific and technical information)
Language(s) - English
Resource type - Reports
DOI - 10.2172/1011665
Subject(s) - dataflow , computer science , suite , spec# , integer (computer science) , latency (audio) , floating point , parallel computing , integer programming , computer architecture , embedded system , operating system , programming language , algorithm , telecommunications , archaeology , history
Scientific applications use highly specialized data structures that require complex, latency sensitive graphs of integer instructions for memory address calculations. Working with the Univeristy of Wisconsin, we have demonstrated significant differences between the Sandia's applications and the industry standard SPEC-FP (standard performance evaluation corporation-floating point) suite. Specifically, integer dataflow performance is critical to overall system performance. To improve this performance, we have developed a configurable functional unit design that is capable of accelerating integer dataflow

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